SH7616 Datasheet, PDF (415/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.2.8 PHY Interface Status Register (PSR)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
LMON
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
PSR enables interface signals from the PHY-LSI to be read.
Bits 31 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0— Link Monitor (LMON): The link status can be read by connecting the LINK signal output
from the PHY-LSI. For information on the polarity, refer to the specifications for the PHY-LSI to
be connected.
Note: The LMON bit is set to 0 when the LNKSTA pin is at high level, and it is set to 1 when
the LNKSTA pin is at low level.
Rev. 2.00 Mar 09, 2006 page 389 of 906
REJ09B0292-0200