SH7616 Datasheet, PDF (765/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Pφ
TCNT
input clock
TCNT
(underflow)
Underflow signal
H'0000
Section 17 16-Bit Timer Pulse Unit (TPU)
H'FFFF
TCFU flag
TCIU interrupt
Figure 17.41 TCIU Interrupt Setting Timing
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 17.42 shows the
timing for status flag clearing by the CPU, and figure 17.43 shows the timing for status flag
clearing by the DMAC.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 17.42 Timing for Status Flag Clearing by CPU
Rev. 2.00 Mar 09, 2006 page 739 of 906
REJ09B0292-0200