SH7616 Datasheet, PDF (327/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
7.5.4 Single Reads
When a cache area is accessed and there is a cache miss, the cache fill cycle is performed in 16-
byte units. This means that all the data read in the burst read is valid. On the other hand, when a
cache-through area is accessed the required data is a maximum length of 32 bits, and the
remaining 12 bytes are wasted. The same kind of wasted data access is produced when
synchronous DRAM is specified as the source in a DMA transfer by the DMAC and the transfer
unit is other than 16 bytes. Figure 7.24 (a) and (b) show the timings of a single address read.
Because the synchronous DRAM is set to the burst read mode, the read data output continues after
the required data is received. To avoid data conflict, an empty read cycle is performed from Td2 to
Td4 after the required data is read in Td1 and the device waits for the end of synchronous DRAM
operation.
When the data width is 16 bits, the number of burst transfers during a read is 8. Data is fetched in
cache-through and other DMA read cycles only in the Td1 and Td2 cycles (of the 8 cycles from
Td1 to Td8) for longword accesses, and only in the Td1 cycle for word or byte accesses.
Empty cycles tend to increase the memory access time, lower the program execution speed, and
lower the DMA transfer speed, so it is important to avoid accessing unnecessary cache-through
areas and to use data structures that enable 16-byte unit transfers by placing data on 16-byte
boundaries when performing DMA transfers that specify synchronous DRAM as the source.
Rev. 2.00 Mar 09, 2006 page 301 of 906
REJ09B0292-0200