SH7616 Datasheet, PDF (677/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
Bit 8—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in SITDR and
resets it to empty status. Also initializes the TERR and TDRE bits in SISTR.
Note that SICTR is not initialized, so transmitting continues if the TE bit is set to 1.
Bit 8: TFRST
Description
0
Reset disabled
(Initial value)
1
Reset enabled
Note: Reset status persists while this bit is set to 1. Clear this bit to 0 to cancel reset status.
Bit 7 to 4—Receive FIFO Watermark (RFWM3 to RFWM0): These bits are used to make
threshold settings, which are used to set the RDRF bit in SISTR.
When the amount of primary receive data in SIRDR is equal to or greater than the watermark
setting, as shown in the table below, the RDRF bit is set to 1.
Bit 7: RFWM3 Bit 6: RFWM2
0
0
1
1
0
1
Bit 5: RFWM1
0
1
0
1
0
1
0
1
Bit 4: RFWM0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Watermark setting
1
(Initial value)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Rev. 2.00 Mar 09, 2006 page 651 of 906
REJ09B0292-0200