SH7616 Datasheet, PDF (128/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.42 Logical Shift Operation Instructions
Instruction
PSHL Sx,Sy,Dz
DCT PSHL
Sx,Sy,Dz
DCF PSHL
Sx,Sy,Dz
PSHL #imm,Dz
Operation
if Sy≥0,Sx<<Sy→Dz, clear
LSW of Dz
if Sy<0,Sx>>Sy→Dz, clear
LSW of Dz
if DC=1 &
Sy≥0,Sx<<Sy→Dz, clear
LSW of Dz
if DC=1 &
Sy<0,Sx>>Sy→Dz, clear
LSW of Dz
if DC=0,nop
if DC=0 &
Sy≥0,Sx<<Sy→Dz, clear
LSW of Dz
if DC=0 &
Sy<0,Sx>>Sy→Dz, clear
LSW of Dz
if DC=1,nop
if imm≥0,Dz<<imm→Dz,
clear LSW of Dz
if imm<0,Dz>>imm→Dz,
clear LSW of Dz
Code
111110**********
10000001xxyyzzzz
Cycles
1
111110********** 1
10000010xxyyzzzz
111110********** 1
10000011xxyyzzzz
111110********** 1
00000iiiiiiizzzz
DC Bit
Update
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Update
Rev. 2.00 Mar 09, 2006 page 102 of 906
REJ09B0292-0200