SH7616 Datasheet, PDF (109/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.24 Branch Instructions
Instruction
Instruction Code
Operation
BF
label 10001011dddddddd If T = 0, disp × 2 + PC → PC,
if T = 1, nop
BF/S
BT
label
label
10001111dddddddd
10001001dddddddd
Delayed branch, if T = 0, disp × 2
+ PC → PC, if T = 1, nop
If T = 1, disp × 2 + PC → PC,
if T = 0, nop
BT/S
label
10001101dddddddd
Delayed branch,
if T = 1, disp × 2 + PC → PC,
if T = 0, nop
BRA label 1010dddddddddddd Delayed branch,
disp × 2 + PC → PC
BRAF
BSR
Rm
label
0000mmmm00100011
1011dddddddddddd
Delayed branch, Rm + PC → PC
Delayed branch, PC → PR,
disp × 2 + PC → PC
BSRF Rm
0000mmmm00000011 Delayed branch,
PC → PR, Rm + PC → PC
JMP @Rm
0100mmmm00101011 Delayed branch, Rm → PC
JSR @Rm
0100mmmm00001011 Delayed branch,
PC → PR, Rm → PC
RTS
0000000000001011 Delayed branch, PR → PC
Note: * One state when it does not branch.
Cycles
3/1^*
2/1^*
3/1^*
2/1^*
2
2
2
2
2
2
2
T Bit
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Rev. 2.00 Mar 09, 2006 page 83 of 906
REJ09B0292-0200