SH7616 Datasheet, PDF (170/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
NMI
IRL3–IRL0
A3–A0
IVECF
D7–D0
Input/
output
control
UBC
H-UDI
DMAC
FRT
WDT
REF
SCIF
TPU
SIO
E-DMAC
(Including EtherC
interrupt)
SIOF
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
ICR
IRQCSR
Priority
decision
logic
Com-
parator
IPR
IPRA–IPRE
Interrupt request
SR
I3 I2 I1 I0
CPU
Module bus
Bus
interface
VCRWDT
VCRWDT, VCRA–VCRU
Vector
number
Vector
number
DMAC
INTC
UBC: User break controller
H-UDI: User debug interface
DMAC: Direct memory access controller
FRT: 16-bit free-running timer
WDT: Watchdog timer
REF: Refresh request within bus state controller
SCIF: Serial communication interface with FIFO
TPU: 16-bit timer pulse unit
SIO: Serial I/O
SIOF: Serial I/O with FIFO
E-DMAC:
Ethernet controller direct memory
access controller
EtherC:
Ethernet controller
ICR:
Interrupt control register
IRQCSR:
IRQ control/status register
IPRA–IPRE: Interrupt priority level setting
registers A–E
VCRWDT: Vector number setting register WDT
VCRA–VCRU: Vector number setting registers A–U
SR:
Status register
Figure 5.1 INTC Block Diagram
Rev. 2.00 Mar 09, 2006 page 144 of 906
REJ09B0292-0200