SH7616 Datasheet, PDF (95/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Parallel Processing Instructions: The parallel processing instructions allow for more efficient
execution of digital signal processing using the DSP unit. They are 32 bit length, allowing
simultaneously in parallel four processes, ALU operations, multiplications or 2 data transfers.
The parallel processing instructions are divided into A fields and B fields. The A field defines data
transfer instructions; the B field defines ALU operation instructions and multiplication
instructions. These instructions can be defined independently, the processes can be independent,
and furthermore, they can be executed simultaneously in parallel. Table 2.17 indicates the A field
parallel data transfer instructions, and table 2.18 indicates the B field ALU operation instructions
and multiplication instructions. A fields instruction is the same as double data transfers in table
2.15.
Table 2.17 A Field Parallel Data Transfer Instructions
Category Mnemonic
31 30 29 28 27 26 25 24 23
X memory NOPX
1111100
0
data
transfers
MOVX.W @Ax,Dx
MOVX.W @Ax+,Dx
Ax
Dx
MOVX.W @Ax+Ix,Dx
MOVX.W Da,@Ax
Da
MOVX.W Da,@Ax+
MOVX.W Da,@Ax+Ix
Y memory NOPY
0
data
transfers
MOVY.W @Ay,Dy
MOVY.W @Ay+,Dy
Ay
MOVY.W @Ay+Iy,Dy
MOVY.W Da,@Ay
MOVY.W Da,@Ay+
MOVY.W Da,@Ay+Iy
Rev. 2.00 Mar 09, 2006 page 69 of 906
REJ09B0292-0200