SH7616 Datasheet, PDF (597/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
SC1SSR is initialized to H'0084 by a reset, by the module standby function, and in standby mode.
Bits 15 to 12—Parity Error Count 3 to 0 (PER3 to PER0): These bits indicate the number of data
bytes in which a parity error occurred in the receive data in the receive FIFO data register.
These bits are cleared by reading all the receive data in the receive FIFO data register, or by
setting the RFRST bit to 1 in SCFCR and resetting the receive FIFO data register to the empty
state.
Bits 11 to 8—Framing Error Count 3 to 0 (FER3 to FER0): These bits indicate the number of data
bytes in which a framing error occurred in the receive data in the receive FIFO data register.
These bits are cleared by reading all the receive data in the receive FIFO data register, or by
setting the RFRST bit to 1 in SCFCR and resetting the receive FIFO data register to the empty
state.
Bit 7—Receive Error (ER)
Bit 7: ER
0
Description
Reception in progress, or reception has ended normally^*1
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When 0 is written to ER after reading ER = 1
1
A framing error, parity error, or overrun error occurred during reception
[Setting conditions]
• When the SCIF checks whether the stop bit at the end of the receive data is
1 when reception ends, and the stop bit is 0^*2
• When, in reception, the number of 1-bits in the receive data plus the parity
bit does not match the parity setting (even or odd) specified by the O/E bit
in the serial mode register (SCSMR)
• When the next serial receive operation is completed while there are 16
receive data bytes in SCFRDR
Notes: 1. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is
cleared to 0. When a framing error or parity error occurs, the receive data is still
transferred to SCFRDR, and reception is then halted or continued according to the
setting of the EI bit. When an overrun error occurs, the receive data is not transferred to
SCFRDR and reception cannot be continued.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit
is not checked.
Rev. 2.00 Mar 09, 2006 page 571 of 906
REJ09B0292-0200