SH7616 Datasheet, PDF (836/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 21 Power-Down Modes
Figure 21.3 shows the clock pause function timing chart when the PLL circuit is halted.
Frequency
modification
CKIO input
CKPREQ/
CKM input
CKPACK
output
Clock pause request
cancellation
Clock pause
acceptance
processing
Clock pause state
Normal state
Figure 21.3 Clock Pause Function Timing Chart (PLL Circuit 1 Halted)
The clock pause state can be canceled by means of NMI input, in the same way as the normal
standby state. The clock pause request should be canceled within four CKIO clock cycles after
NMI input. Figure 21.4 shows the timing chart for clock pause state cancellation by means of NMI
input (in the case of rising edge detection).
Rev. 2.00 Mar 09, 2006 page 810 of 906
REJ09B0292-0200