SH7616 Datasheet, PDF (318/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
For the CS0–CS4 spaces, For spaces CS0—CS4, Th and Tf can be set as follows.
CS0—3
CS4
Th
0—2
0—7
Tf
0—2
0—5
WCR3
AnSW1, AnSW0 (Th = Tf) n =0—3
Th: A4SW2—0
Tf: A4HW1—0
7.5 Synchronous DRAM Interface
7.5.1 Synchronous DRAM Direct Connection
Seven kinds of synchronous DRAM can be connected: 2-Mbit (128 k × 16), 4-Mbit (256 k × 16),
16-Mbit (1 M × 16, 2 M × 8, and 4 M × 4), and 64-Mbit (4 M × 16 and 8 M × 8). This chip
supports 64-Mbit synchronous DRAMs internally divided into two or four banks, and other
synchronous DRAMs internally divided into two banks. Since synchronous DRAM can be
selected by the CS signal, CS2 and CS3 spaces can be connected using a common RAS or other
control signal. When the memory enable bits for DRAM and other memory (DRAM2–DRAM0)
in BCR1 are set to 001, CS2 is ordinary space and CS3 is synchronous DRAM space. When the
DRAM2–0 bits are set to 100, CS2 is synchronous DRAM space and CS3 is ordinary space. When
the bits are set to 101, both CS2 and CS3 are synchronous DRAM spaces.
Supported synchronous DRAM operating modes are burst read/single write mode (initial setting)
and burst read/burst write mode. The burst length depends on the data bus width, comprising 8
bursts for a 16-bit width, and 4 bursts for a 32-bit width. The data bus width is specified by the SZ
bit in MCR. Burst operation is always performed, so the burst enable (BE) bit in MCR is ignored.
Switching to burst write mode is performed by means of the BWE bit in BCR3.
Control signals for directly connecting synchronous DRAM are the RAS, CAS/OE, RD/WR, CS2
or CS3, DQMUU, DQMUL, DQMLU, DQMLL, and CKE signals. Signals other than CS2 and
CS3 are common to every area, and signals other than CKE are valid and fetched only when CS2
or CS3 is true. Therefore, synchronous DRAM can be connected in parallel in multiple areas. CKE
is negated (to the low level) only when a self-refresh is performed; otherwise it is always asserted
(to the high level).
Commands can be specified for synchronous DRAM using the RAS, CAS/OE, RD/WR, and
certain address signals. These commands are NOP, auto-refresh (REF), self-refresh (SELF), all-
bank precharge (PALL), specific bank precharge (PRE), row address strobe/bank active (ACTV),
read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and
mode register write (MRS).
Rev. 2.00 Mar 09, 2006 page 292 of 906
REJ09B0292-0200