SH7616 Datasheet, PDF (161/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

4.4 Interrupts
Section 4 Exception Handling
4.4.1 Interrupt Sources
Table 4.7 shows the sources that initiate interrupt exception handling. These are divided into NMI,
user breaks, H-UDI, IRL, IRQ, and on-chip peripheral modules.
Table 4.7 Types of Interrupt Sources
Type
NMI
User break
H-UDI
IRL
IRQ
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller (UBC)
User debug interface (H-UDI)
IRL1–IRL15 (external input)
IRQ0–IRQ3 (external input)
Direct memory access controller (DMAC)
Ethernet controller (EtherC) and Ethernet
controller direct memory access controller
(E-DMAC)
16-bit free-running timer (FRT)
Watchdog timer (WDT)
Bus state controller (BSC)
Serial I/O with FIFO (SIOF)
Serial I/O (SIO)
Serial communication interface with FIFO
(SCIF)
16-bit timer pulse unit (TPU)
Number of Sources
1
1
1
15
4
2
1
3
1
1
4
4
4
13
Each interrupt source is allocated a different vector number and vector table address offset. See
table 5.4, Interrupt Exception Vectors and Priority Order, in section 5, Interrupt Controller, for
more information.
Rev. 2.00 Mar 09, 2006 page 135 of 906
REJ09B0292-0200