SH7616 Datasheet, PDF (603/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
The MPBT bit setting is invalid in synchronous mode and IrDA mode, when a multiprocessor
format is not used, and when the operation is not transmission.
Bit 2: MPBT
0
1
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
(Initial value)
Bit 1—Receive Data Error Ignore Enable (EI): Selects whether or not the receive operation is to
be continued when a framing error or parity error occurs in receive data (ER = 1).
Bit 1: EI
Description
0
Receive operation is halted when framing error or parity error occurs during
reception (ER = 1)
(Initial value)
1
Receive operation is continued when framing error or parity error occurs during
reception (ER = 1)
Note: When EI = 0, only the last data in SCFRDR is treated as data containing an error. When EI
= 1, receive data is sent to SCFRDR even if it contains an error.
Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing
abnormal termination.
Bit 0: ORER
0
Description
Reception in progress, or reception has ended normally^*1
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When 0 is written to ORER after reading ORER = 1
1
An overrun error occurred during reception^*2
[Setting condition]
When the next serial receive operation is completed while there are 16 receive
data bytes in SCFRDR
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR
is cleared to 0.
2. The receive data prior to the overrun error is retained in SCFRDR, and the data
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1. Also, serial transmission cannot be continued in synchronous mode.
Rev. 2.00 Mar 09, 2006 page 577 of 906
REJ09B0292-0200