SH7616 Datasheet, PDF (271/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
Set conditions:
Channels A and B independent, channel C → channel D sequential mode
Channel A: Not used
Channel B: Not used
Channel C: Address: H'00037226; address mask: H'00000000
Data:
H'00000000; data mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution), write, word
Channel D: Address: H'0003722E; address mask: H'00000000
Data:
H'00000000; data mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution), read, word
As the channel C break condition is a write cycle, the condition is not matched, and as the
sequential conditions are not satisfied, a user break interrupt is not generated.
D. Register settings: BBRA = H'0000
BARB = H'00000500 / BAMRB = H'00000000 / BBRB = H'0057
BARC = H'00000A00 / BAMRC = H'00000000 / BBRC = H'0057
BDRC = H'00000000 / BDMRC = H'00000000
BARD = H'00001000 / BAMRD = H'00000000 / BBRD = H'0057
BDRD = H'00000000 / BDMRD = H'00000000
BRCR = H'00102020 / BETRC = H'0005 / BETRD = H'000A
Channel A: Not used
Channel B: Address: H'00000500; address mask: H'00000000
Data:
H'00000000; data mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Channel C: Address: H'00000A00; address mask: H'00000000
Data:
H'00000000; data mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Execution-times break enabled (5 times)
Channel D: Address: H'00001000; address mask: H'00000000
Data:
H'00000000; data mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Execution-times break enabled (10 times)
Rev. 2.00 Mar 09, 2006 page 245 of 906
REJ09B0292-0200