SH7616 Datasheet, PDF (73/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.5 Destination Register Data Formats for DSP Instructions
Register
A0, A1
A0G, A1G
X0, X1, Y0,
Y1, M0, M1
Instruction
DSP
operation
Fixed
decimal,
PSHA,
PMULS
Integer,
PDMSB
Logic, PSHL
Data transfer MOVS.W
MOVS.L
Data transfer MOVS.W
MOVS.L
DSP
operation
Fixed
decimal,
PSHA,
PMULS
Integer, logic,
PDMSB,
PSHL
Data transfer
MOVX.W,
MOVY.W,
MOVS.W
MOVS.L
Guard Bits
39–32
(Sign extend)
Clear to 0
Sign extend
Data
—
Register Bits
31–16
15–0
40-bit result
24-bit result
16-bit result
Clear to 0
32-bit data
Not updated
Not updated
32-bit result
16-bit result Clear to 0
32-bit data
Rev. 2.00 Mar 09, 2006 page 47 of 906
REJ09B0292-0200