SH7616 Datasheet, PDF (559/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 12 16-Bit Free-Running Timer (FRT)
12.4.4 Input Capture Input Timing
Either the rising edge or falling edge can be selected for input capture input using the IEDG bit in
TCR. Figure 12.8 shows the timing when the rising edge is selected (IEDG = 1).
Pφ
Input capture
input pin
Input capture
signal
Figure 12.8 Input Capture Signal Timing (Normal)
When the input capture signal is input when FICR is read (upper-byte read), the input capture
signal is delayed by one cycle of Pφ. Figure 12.9 shows the timing.
FICR upper-byte read cycle
Pφ
Input capture
input pin
Input capture
signal
Figure 12.9 Input Capture Signal Timing (Input Capture Input when FICR is Read)
Rev. 2.00 Mar 09, 2006 page 533 of 906
REJ09B0292-0200