SH7616 Datasheet, PDF (469/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.2.13 E-DMAC Operation Control Register (EDOCR)
EDOCR specifies the control methods used in E-DMAC operation.
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
FEC AEC EDH
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W
R/W
R/W
R
Bits 31 to 4, and 0—Reserved: These bits are always read as 0. The write value should always be
0.
Bit 3—FIFO Error Control (FEC): Specifies E-DMAC operation when transmit FIFO underflow
or receive FIFO overflow occurs.
Bit 3: FEC
0
1
Description
E-DMAC operation continues when underflow or overflow occurs (Initial value)
E-DMAC operation halts when underflow or overflow occurs
Bit 2—Address Error Control (AEC): Indicates detection of an illegal memory address in an
attempted E-DMAC transfer.
Bit 2: AEC
Description
0
Illegal memory address not detected (normal operation)
(Initial value)
1
Illegal memory address detected. Can be cleared by writing 0
Note: This error occurs if the memory address setting in the descriptor used by the E-DMAC is
illegal.
Bit 1—E-DMAC Halted (EDH): When the SH7616’s NMI input pin is asserted, E-DMAC
operation is halted.
Bit 1: EDH
0
1
Description
The E-DMAC is operating normally
(Initial value)
The E-DMAC has been halted by NMI pin assertion. E-DMAC operation is
restarted by writing 0
Rev. 2.00 Mar 09, 2006 page 443 of 906
REJ09B0292-0200