SH7616 Datasheet, PDF (302/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
is 0, a CAS-before-RAS refresh or auto-refresh is performed at the interval set in the 8-bit interval
timer. When a refresh request occurs during an external area access, the refresh is performed after
the access cycle is completed. When set for self-refresh, self-refresh mode is entered immediately
unless the chip is in the middle of a synchronous DRAM area access, in which case self-refresh
mode is entered when the access ends. Refresh requests from the interval timer are ignored during
self-refresh.
Bit 2: RMODE
0
1
Description
Normal refresh
Self-refresh
(Initial value)
7.2.8 Refresh Timer Control/Status Register (RTCSR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
CMF
0
R/W
6
CMIE
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
2
RRC2
0
R/W
1
RRC1
0
R/W
0
RRC0
0
R/W
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Compare Match Flag (CMF): This status flag, which indicates that the values of RTCNT
and RTCOR match, is set/cleared under the following conditions:
Bit 7: CMF
0
1
Description
[Clearing condition]
After RTCSR is read when CMF is 1, 0 is written in CMF
[Setting condition]
RTCNT = RTCOR
Rev. 2.00 Mar 09, 2006 page 276 of 906
REJ09B0292-0200