SH7616 Datasheet, PDF (140/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 3 Oscillator Circuits and Operating Modes
3.2.5 Operating Frequency Selection by Register
Using the frequency modification register (FMR), it is possible to specify the operating frequency
division ratio for the internal clocks (Iφ, Eφ, Pφ). The internal clock frequency is determined under
the control of PLL circuits 1 and 2 and dividers DIVM, DIVE, and DIVP.
Frequency Modification Register (FMR): The frequency modification register is initialized only
by a power-on reset via the RES pin, and not by an internal reset resulting from WDT overflow.
Its initial value depends on the settings of pins MD2–MD0. Table 3.4 shows the relationship
between the MD2–MD0 pin combinations and the initial value of the frequency modification
register.
Table 3.4 Relationship between Clock Mode Pin Settings and Initial Value of Frequency
Modification Register
Clock Mode
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
MD2
0
0
0
0
1
1
1
MD1
0
0
1
1
0
0
1
MD0
0
1
0
1
0
1
0
Initial Value
H'00
H'40
H'60
H'A6
H'E0
The register configuration is shown in table 3.5.
Table 3.5 Register Configuration
Name
Abbreviation R/W
Frequency modification register FMR
R/W
Note: * The initial value depends on the clock mode.
Initial Value
See table 3.4^*
Address
H'FFFFFE90
Rev. 2.00 Mar 09, 2006 page 114 of 906
REJ09B0292-0200