SH7616 Datasheet, PDF (769/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Compare Match: If a compare match occurs in the T2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 17.47 shows the timing in this case.
Pφ
Address
TGR write cycle
T1
T2
TGR address
Write signal
Compare
match signal
TCNT
Inhibited
N
N+1
TGR
N
M
TGR write data
Figure 17.47 Contention between TGR Write and Compare Match
Rev. 2.00 Mar 09, 2006 page 743 of 906
REJ09B0292-0200