SH7616 Datasheet, PDF (602/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Bit 7—Transmit LSB/MSB-First Select (TLM): Selects LSB-first or MSB-first mode in data
transmission.
Bit 7: TLM
0
1
Description
LSB-first transmission
MSB-first transmission
(Initial value)
Bit 6—Receive LSB/MSB-First Select (RLM): Selects LSB-first or MSB-first mode in data
reception.
Bit 6: RLM
0
1
Description
LSB-first reception
MSB-first reception
(Initial value)
Bits 5 and 4—Clock Bit Rate Ratio (N1, N0): These bits select the ratio of the base clock to the bit
rate.
Bit 5:
N1
0
1
Bit 4:
N0
0
1
0
1
Description
SCIF operates on base clock of 4 times the bit rate
SCIF operates on base clock of 8 times the bit rate
SCIF operates on base clock of 16 times the bit rate
Setting prohibited
(Initial value)
Bit 3—Multiprocessor bit (MPB): When reception is performed using a multiprocessor format in
asynchronous mode, MPB stores the multiprocessor bit in the receive data.
The MPB flag is read-only and cannot be modified.
Bit 3: MPB
Description
0
Data with a 0 multiprocessor bit has been received^*
(Initial value)
1
Data with a 1 multiprocessor bit has been received
Note: ^* Retains its previous state when the RE bit is cleared to 0 while using a multiprocessor
format.
Bit 2—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
Rev. 2.00 Mar 09, 2006 page 576 of 906
REJ09B0292-0200