SH7616 Datasheet, PDF (423/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.2.16 Frame Receive Error Counter Register (FRECR )
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
FREC15 FREC14 FREC13 FREC12 FREC11 FREC10 FREC9
Initial value: 0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
FREC8
0
R/W
Bit:
Initial value:
R/W:
7
FREC7
0
R/W
6
FREC6
0
R/W
5
FREC5
0
R/W
4
FREC4
0
R/W
3
FREC3
0
R/W
2
FREC2
0
R/W
1
FREC1
0
R/W
0
FREC0
0
R/W
FRECR is a 16-bit counter that indicates the number of frames input from the PHY-LSI for which
a receive error was indicated by the RX-ER pin. FRECR is incremented each time this pin
becomes active. When the value in this register reaches H'FFFF (65,535), the count is halted. The
counter value is cleared to 0 by a write to this register (the write value is immaterial).
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—Frame Receive Error Count 15 to 0 (FREC15 to FREC0): These bits indicate the
count of errors during frame reception.
Rev. 2.00 Mar 09, 2006 page 397 of 906
REJ09B0292-0200