SH7616 Datasheet, PDF (697/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 16 Serial I/O (SIO)
16.2.5 Serial Control Register (SICTR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
TM
SE
DL
TIE
RIE
TE
RE
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SICTR is a 16-bit register used to set parameters for serial port control. SICTR is initialized to
H'0000 by a reset.
When modifying bit 4, 5, or 6 (TM, SE, or DL), TE and RE should be cleared to 0 beforehand.
Bits 15 to 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 6—Transfer Mode Control (TM): Specifies whether the transmission synchronization signal is
to be input from an external source or generated internally by the chip. When this flag is cleared,
the transmission synchronization signal is STS pin input. When this flag is set, the transmission
synchronization signal is generated by the chip, and is output to an external device from the STS
pin. This bit does not affect reception.
Bit 6: TM
0
1
Description
External signal input from STS pin is used as transmission start indication
(Initial value)
Internal signal output from STS pin is used as transmission start indication
Bit 5—Synchronization Signal Enable (SE): Specifies whether the synchronization signals are to
be used for all serial data transfers, or only for the first transfer.
When this bit is cleared to 0, the synchronization signals (SRS and STS) are necessary only for the
first data transfer, and are not required for subsequent transfers. When this bit is set to 1, the
synchronization signals are necessary for all data transfers.
Bit 5: SE
0
1
Description
Continuous mode: SRS and STS are used only for the first data transfer
(Initial value)
Interval mode: SRS and STS are used for all data transfers
Rev. 2.00 Mar 09, 2006 page 671 of 906
REJ09B0292-0200