SH7616 Datasheet, PDF (344/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
CKIO
Tp
Trr
Trc
Trc
Trc
Tre
A10
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
Figure 7.33 Auto-Refresh Timing
Self-Refreshes: The self-refresh mode is a type of standby mode that produces refresh timing and
refresh addresses within the synchronous DRAM. It is started up by setting the RMODE and
RFSH bits to 1. The synchronous DRAM is in self-refresh mode when the CKE signal level is
low. During the self-refresh, the synchronous DRAM cannot be accessed. To clear the self-refresh,
set the RMODE bit to 0. After self-refresh mode is cleared, issuing of commands is prohibited for
the number of cycles specified in the TRAS1 and TRAS0 bits in MCR. Figure 7.34 shows the self-
refresh timing. Settings must be made so that self-refresh clearing and data retention are
performed correctly, and auto-refreshing is performed without delay at the correct intervals. When
self-refresh mode is entered while the synchronous DRAM is set for auto-refresh or when leaving
the standby mode with a manual reset or NMI, auto-refresh can be re-started if RFSH is 1 and
RMODE is 0 when the self-refresh mode is cleared. When time is required between clearing the
self-refresh mode and starting the auto-refresh mode, this time must be reflected in the initial
RTCNT setting. When the RTCNT value is set to RTCOR – 1, the refresh can be started
immediately.
If the standby function of the chip is used to enter the standby mode after the self-refresh mode is
set, the self-refresh state continues; the self-refresh state will also be maintained after returning
from a standby using an NMI. A manual reset cannot be used to exit the self-refresh state either.
During a power-on reset, the bus state controller register is initialized, so the self-refresh state is
ended.
Rev. 2.00 Mar 09, 2006 page 318 of 906
REJ09B0292-0200