SH7616 Datasheet, PDF (235/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
BAMRBL Bits 15 to 0—Break Address Mask B15 to B0 (BAMB15 to BAMB0): These bits
specify whether or not corresponding channel B break address bits 15 to 0 (BAB15 to BAB0) set
in BARBL are to be masked.
Bit 31 to 0:
BAMBn
Description
0
Channel B break address bit BABn is included in break condition (Initial value)
1
Channel B break address bit BABn is masked, and not included in condition
Note: n = 31 to 0
6.2.6 Break Bus Cycle Register B (BBRB)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
CPB1
0
R/W
6
CPB0
0
R/W
5
IDB1
0
R/W
4
IDB0
0
R/W
3
RWB1
0
R/W
2
RWB0
0
R/W
1
SZB1
0
R/W
0
SZB0
0
R/W
Break bus cycle register B (BBRB) is a 16-bit readable/writable register that sets four channel B
break conditions: (1) CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (2) instruction
fetch/data access, (3) read/write, and (4) operand size. BBRB is initialized to H'0000 by a power-
on reset; after a manual reset, its value is undefined.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU/DMAC, E-DMAC Cycle Select B (CPB1, CPB0): These bits specify whether
a CPU cycle, or a DMAC or E-DMAC cycle, is to be selected as the bus cycle used as a channel B
break condition.
Bit 7:
CPB1
0
1
Bit 6:
CPB0
0
1
0
1
Description
Channel B user break interrupt is not generated
(Initial value)
CPU cycle is selected as user break condition
DMAC or E-DMAC cycle is selected as user break condition
CPU, DMAC, or E-DMAC cycle is selected as user break condition
Rev. 2.00 Mar 09, 2006 page 209 of 906
REJ09B0292-0200