SH7616 Datasheet, PDF (263/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.3.2 Instruction Fetch Cycle Break
1. If a CPU/instruction fetch/read/word setting is made in the break bus cycle register (BBRA,
BBRB, BBRC, or BBRD), a CPU instruction fetch cycle can be selected as a break condition.
In this case, it is possible to specify whether the break is to be effected before or after
execution of the relevant instruction by means of the PCBA/PCBB/PCBC/PCBD bit in the
break control register (BRCR).
2. In the case of an instruction for which pre-execution is set as the break condition, the break is
performed when it has been confirmed that the instruction has been fetched and is to be
executed. Consequently, a break cannot be set for an overrun-fetched instruction (an
instruction fetched but not executed in the event of a branch or interrupt transition). If a break
is set for the delay slot of a delayed branch instruction, or for the instruction following an
instruction for which interrupts are prohibited, such as LCD, an interrupt is generated before
execution of the next instruction at which interrupts are accepted.
3. With the post-execution condition, an interrupt is generated after execution of the instruction
set as the break condition, and before execution of the following instruction. As in 2 above, a
break cannot be set for an overrun-fetched instruction. If a break is set for a delayed branch
instruction, or for an instruction for which interrupts are prohibited, such as LCD, an interrupt
is generated before execution of the next instruction at which interrupts are accepted.
4. When an instruction fetch cycle is set for channel C or D, break data register C (BDRC) or
break data register D (BDRD) is ignored. Therefore, break data need not be set for an
instruction fetch cycle break.
5. When an instruction fetch cycle is set, the start address at which that instruction is located
should be set for the break. A break will not occur if a different address is set. Also, a break
will not occur if the address of the lower word of a 32-bit instruction is set.
Rev. 2.00 Mar 09, 2006 page 237 of 906
REJ09B0292-0200