SH7616 Datasheet, PDF (770/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
write data.
Figure 17.48 shows the timing in this case.
TGR write cycle
T1
T2
Pφ
Address
Buffer register
address
Write signal
Compare
match signal
Buffer
register
Buffer register write data
N
M
TGR
M
Figure 17.48 Contention between Buffer Register Write and Compare Match
Rev. 2.00 Mar 09, 2006 page 744 of 906
REJ09B0292-0200