SH7616 Datasheet, PDF (246/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
BARD Configuration
Upper 16 Bits
(BAD31 to BAD16)
Lower 16 Bits
(BAD15 to BAD0)
XYED = 0 Address
Upper 16 bits of address bus Lower 16 bits of address bus
XYED = 1 X address
X address
—
(when XYSD = 0) (XAB15 to XAB1)^*
Y address
—
(when XYSD = 1)
Y address
(YAB15 to YAB1)^*
Note: * As an X/Y bus access is always a word access, the values of XAB0 and YAB0 is not
included in the break condition.
6.2.14 Break Address Mask Register D (BAMRD)
BAMRDH
Bit: 15
14
13
12
11
10
9
8
BAMD31 BAMD30 BAMD29 BAMD28 BAMD27 BAMD26 BAMD25 BAMD24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
BAMD23 BAMD22 BAMD21 BAMD20 BAMD19 BAMD18 BAMD17 BAMD16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BAMRDL
Bit: 15
14
13
12
11
10
9
8
BAMD15 BAMD14 BAMD13 BAMD12 BAMD11 BAMD10 BAMD9 BAMD8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
7
BAMD7
0
R/W
6
BAMD6
0
R/W
5
BAMD5
0
R/W
4
BAMD4
0
R/W
3
BAMD3
0
R/W
2
BAMD2
0
R/W
1
BAMD1
0
R/W
0
BAMD0
0
R/W
Rev. 2.00 Mar 09, 2006 page 220 of 906
REJ09B0292-0200