SH7616 Datasheet, PDF (393/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 8 Cache
reason, this cache uses a pseudo-LRU replacement algorithm that keeps track of the order of way
access and replaces the oldest way.
Six bits of data are used as the LRU information. The bits indicate the access order for 2 ways, as
shown in figure 8.10. When the value is 1, access occurred in the direction of the appropriate
arrow in the figure. The direction of the arrow can be determined by reading the bit. Access to the
way to which all the arrows are pointing is the oldest, and that way becomes subject to
replacement. The access order is recorded in the LRU information bits, so the LRU information is
rewritten when a cache hit occurs during a read, when a cache hit occurs during a write, and when
replacement occurs after a cache miss. Table 8.3 shows the rewrite values; table 8.4 shows how
the way to be replaced is selected.
After a cache purge by means of the CP bit in CCR, all the LRU information is zeroized, so the
initial order of use is way 3 → way 2 → way 1 → way 0. Thereafter, the way is selected according
to the order of access in the program. Since the replacement will not be correct if the LRU gets an
inappropriate value, the address array write function can be used to rewrite. When this is done, be
sure not to write a value other than 0 as the LRU information.
When the OD bit or ID bit in CCR is 1, cache replacement is not performed even if a cache miss
occurs during data read or instruction fetch. Instead of replacing, the missed address data is read
and directly transferred to the CPU.
The two-way mode of the cache set by CCR’s TW bit can only be implemented by replacing ways
2 and 3. Comparisons of address array tag addresses are carried out on all four ways even in two-
way mode, so the valid bits of ways 1 and 0 must be cleared to 0 before beginning operation in
two-way mode.
Writing for the tag address and valid bit for cache replacement does not wait for the read from
memory to be completed. If a memory access is aborted due to a reset, etc., during replacement,
there will be a discrepancy between the cache contents and memory contents, so a purge must be
performed.
Way 0
Bit 5
Way 1
Bit 1
Bit 4
Bit 3
Way 3
Bit 2
Way 2
Bit 0
Figure 8.10 LRU Information and Access Sequence
Rev. 2.00 Mar 09, 2006 page 367 of 906
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