SH7616 Datasheet, PDF (656/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
14.4 SCIF Interrupt Sources and the DMAC
The SCIF has four interrupt sources: the break interrupt (BRI) request, receive-error interrupt
(ERI) request, receive-FIFO-data-full interrupt (RXI) request, and transmit-FIFO-data-empty
interrupt (TXI) request.
Table 14.13 shows the interrupt sources and their relative priorities. The interrupt sources can be
enabled or disabled with the TIE or RIE bit in SCSCR. Each kind of interrupt request is sent to the
interrupt controller independently.
When the TDFE flag is set to 1 in the serial status 1 register (SC1SSR), a TXI interrupt is
requested. A TXI interrupt request can activate the DMAC to perform data transfer. The TDFE bit
is cleared to 0 automatically when all writes to the transmit FIFO data register (SCFTDR) by the
DMAC are completed.
When the RDF flag is set to 1 in SC1SSR, an RXI interrupt is requested. An RXI interrupt request
can activate the DMAC to perform data transfer. The RDF bit is cleared to 0 automatically when
all receive FIFO data register (SCFRDR) reads by the DMAC are completed.
When the ER flag is set to 1, an ERI interrupt is requested. The DMAC cannot be activated by an
ERI interrupt request.
When the BRK flag is set to 1, a BRI interrupt is requested. The DMAC cannot be activated by a
BRI interrupt request.
A TXI interrupt indicates that transmit data can be written, and an RXI interrupt indicates that
there is receive data in SCFRDR.
Table 14.13 SCIF Interrupt Sources
Interrupt Source
ERI
RXI
Description
Receive error (ER)
Receive data full (RDF) or data ready (DR)
BRI
Break (BRK)
TXI
Transmit data FIFO empty (TDFE)
DMAC
Activation
Not possible
Possible
(RDF only)
Not possible
Possible
Priority on
Reset Release
High
↑
↓
Low
Rev. 2.00 Mar 09, 2006 page 630 of 906
REJ09B0292-0200