SH7616 Datasheet, PDF (406/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.2 Register Descriptions
9.2.1 EtherC Mode Register (ECMR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
— PRCEF —
—
MPDE
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R
R
R/W
R
Bit:
7
6
5
4
3
2
1
0
—
RE
TE
—
ILB
ELB
DM
PRM
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W
R/W
R
R/W
R/W
R/W
R/W
The EtherC mode register specifies the operating mode of the Ethernet controller. The settings in
this register are normally made in the initialization process following a reset.
Notes: Operation mode settings must not be changed while the transmitting and receiving
functions are enabled. To modify bits other than the ECMR's RE and TE bits, follow the
procedures below.
1. Return EtherC and E-DMAC to their initial state by means of the software reset bit
(SWR) in the E-DMAC mode register (EDMR), and make new settings.
2. Set the RE and TE bits to 0 to disable them before modifying bits. Since a frame may
be transmitted or received, wait for at least a maximum frame transfer time before
changing bits other than the RE and TE bits.
Bits 31 to 13—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 380 of 906
REJ09B0292-0200