SH7616 Datasheet, PDF (465/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.2.10 Transmit FIFO Threshold Register (TFTR)
TFTR specifies the transmit FIFO threshold at which the first transmission is started. The actual
threshold is 4 times the set value. The EtherC starts transmission when the amount of data in the
transmit FIFO exceeds the number of bytes specified by this register, when the transmit FIFO is
full, or when 1-frame write is executed.
Note: When setting this register, do so in the transmission-halt state.
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
TFT10 TFT9 TFT8
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W
R/W
R/W
Bit:
Initial value:
R/W:
7
TFT7
0
R/W
6
TFT6
0
R/W
5
TFT5
0
R/W
4
TFT4
0
R/W
3
TFT3
0
R/W
2
TFT2
0
R/W
1
TFT1
0
R/W
0
TFT0
0
R/W
Bits 31 to 11—Reserved: These bits should only be written with 0.
Rev. 2.00 Mar 09, 2006 page 439 of 906
REJ09B0292-0200