SH7616 Datasheet, PDF (783/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 18 User Debug Interface (H-UDI)
18.3.2 Status Register (SDSR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
1
1
1
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— SDTRF
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R
R/W
The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. Output
from TDO is possible for SDSR, but serial data cannot be written to SDSR via TDI. The SDTRF
bit is output by means of a 1-bit shift. In the case of a 2-bit shift, the SDTRF bit is first output,
followed by a reserved bit.
SDSR is initialized by TRST signal input, but is not initialized by a reset or in standby mode.
Bits 15 to 1—Reserved: Bits 15 to 11 and 7 to 1 are always read as 0, and the write value should
always be 0. Bits 10 to 8 are always read as 1, and the write value should always be 1.
Bit 0—Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be
accessed by the CPU. The SDTRF bit is reset by the TRST signal , but is not initialized by a reset
or in standby mode.
Bit 0: SDTRF
0
1
Description
Serial transfer to SDDR has ended, and SDDR can be accessed
Serial transfer to SDDR in progress
(Initial value)
Rev. 2.00 Mar 09, 2006 page 757 of 906
REJ09B0292-0200