SH7616 Datasheet, PDF (550/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 12 16-Bit Free-Running Timer (FRT)
Bits 6 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects enabling/disabling of the OCIA
interrupt request when the output compare flag A (OCFA) in FTCSR is set to 1.
Bit 3: OCIAE
0
1
Description
Interrupt request (OCIA) caused by OCFA disabled
Interrupt request (OCIA) caused by OCFA enabled
(Initial value)
Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects enabling/disabling of the OCIB
interrupt request when the output compare flag B (OCFB) in FTCSR is set to 1.
Bit 2: OCIBE
0
1
Description
Interrupt request (OCIB) caused by OCFB disabled
Interrupt request (OCIB) caused by OCFB enabled
(Initial value)
Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects enabling/disabling of the OVI interrupt
request when the overflow flag (OVF) in FTCSR is set to 1.
Bit 1: OVIE
0
1
Description
Interrupt request (OVI) caused by OVF disabled
Interrupt request (OVI) caused by OVF enabled
(initial value)
Bit 0—Reserved: This bit is always read as 1. The write value should always be 1.
12.2.5 Free-Running Timer Control/Status Register (FTCSR)
Bit: 7
6
5
4
3
2
1
0
ICF
—
—
—
OCFA OCFB OVF CCLRA
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)^*
R
R
R
R/(W)^* R/(W)^* R/(W)^* R/W
Note: * For bits 7, and 3 to 1, the only value that can be written is 0 (to clear the flags).
FTCSR is an 8-bit register that selects counter clearing and controls interrupt request signals.
FTCSR is initialized to H'00 by a reset, in standby mode, and when the module standby function is
used. See section 12.4, Operation, for the timing.
Rev. 2.00 Mar 09, 2006 page 524 of 906
REJ09B0292-0200