SH7616 Datasheet, PDF (160/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 4 Exception Handling
4.3.2 Address Error Exception Handling
When an address error occurs, address error exception handling begins after the end of the bus
cycle in which the error occurred and completion of the executing instruction. The CPU operates
as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last instruction executed .
3. The exception service routine start address is fetched from the exception vector table entry that
corresponds to the address error that occurred, and the program starts executing from that
address. The jump that occurs is not a delayed branch.
Note: The same vector number, 10, is generated for a DMAC DMA address error and an E-
DMAC DMA address error. (See table 4.3 (a).)
Both the address error flag (AE) in the DMAC’s DMA operation register (DMAOR) and
the address error control bit (AEC) in the E-DMAC’s E-DMAC operation control register
(EDOCR) must therefore be read in the exception service routine to determine which
DMA address error has occurred.
Rev. 2.00 Mar 09, 2006 page 134 of 906
REJ09B0292-0200