SH7616 Datasheet, PDF (539/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.8 DMA Transfer End
The DMA transfer ending conditions vary when channels end individually and when both
channels end together.
Conditions for Channels Ending Individually: When either of the following conditions is met,
the transfer will end in the relevant channel only:
The DMA transfer count register (TCR) value becomes 0.
The DMA enable bit (DE) of the DMA channel control register (CHCR) is cleared to 0.
• Transfer end when TCR = 0
When the TCR value becomes 0, the DMA transfer for that channel ends and the transfer-end
flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has already been set, a DMAC
interrupt (DEI) request is sent to the CPU. For 16-byte transfer, set the number of transfers × 4.
Operation is not guaranteed if an incorrect value is set.
A 16-byte transfer is valid only in auto-request mode or in external request mode with edge
detection. When using an external request with level detection or on-chip peripheral module
request, do not specify a 16-byte transfer.
• Transfer end when DE = 0 in CHCR
When the DMA enable bit (DE) in CHCR is cleared, DMA transfers in the affected channel
are halted. The TE bit is not set when this happens.
Conditions for Both Channels Ending Simultaneously: Transfers on both channels end when
either of the following conditions is met:
The NMIF (NMI flag) bit or AE (address error flag) bit in DMAOR is set to 1.
The DMA master enable (DME) bit is cleared to 0 in DMAOR.
• Transfer end when NMIF = 1 or AE = 1 in DMAOR
When an NMI interrupt or DMAC address error occurs and the NMIF or AE bit is set to 1 in
DMAOR, all channels stop their transfers. The DMA source address register (SAR),
destination address register (DAR), and transfer count register (TCR) are all updated by the
transfer immediately preceding the halt. When this transfer is the final transfer, TE = 1 and the
transfer ends. To resume transfer after NMI interrupt exception handling or address error
exception handling, clear the appropriate flag bit. When the DE bit is then set to 1, the transfer
on that channel will restart. To avoid this, keep its DE bit at 0. In dual address mode, DMA
transfer will be halted after the completion of the following write cycle even when the address
error occurs in the initial read cycle. SAR, DAR and TCR are updated by the final transfer.
Rev. 2.00 Mar 09, 2006 page 513 of 906
REJ09B0292-0200