SH7616 Datasheet, PDF (517/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TB bits in
CHCR0 and CHCR1.
• Cycle-Steal Mode
In cycle-steal mode, the bus right is given to another bus master each time the DMAC
completes one transfer. When another transfer request occurs, the bus right is retrieved from
the other bus master and another transfer is performed for one transfer unit. When that transfer
ends, the bus right is passed to the other bus master. This is repeated until the transfer end
conditions are satisfied. (in the case of 16-byte transfer in dual address mode, the DMAC
continues to hold the bus)
Cycle-steal mode can be used with all categories of transfer destination, transfer source, and
transfer request source. (with the exception of transfers between on-chip peripheral modules)
The CPU may take the bus twice when an acknowledge signal is output during the write cycle
or in single address mode. Figure 11.10 shows an example of DMA transfer timing in cycle-
steal mode. The transfer conditions for the example in the figure are as shown below.
When the transfer request source is an external request mode with level detection in the cycle-
steal mode, set the TS1 and TS0 bits of CHCR0 and CHCR1 to either 00 (byte unit), 01 (word
unit), or 01 (longword unit). If the TS1 and TS0 bits of CHCR0 and CHCR1 are set to 11 (16-
byte transfer), operation is not guaranteed.
• Dual address mode
• DREQn level detection
DREQn
Bus
cycle
CPU
Bus right returned to CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU
Read Write
Read Write
Figure 11.10 DMA Transfer Timing in Cycle-Steal Mode
(Dual Address Mode, DREQn Low Level Detection)
Rev. 2.00 Mar 09, 2006 page 491 of 906
REJ09B0292-0200