SH7616 Datasheet, PDF (861/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 22 Electrical Characteristics
CKIO
Address
upper bits
Address
lower bits
BS
CSn
RD/WR
T_p
t_AD
t_BSD
t_CSD1
t_RWD
T_r
t_RWD
T_c
t_AD
T_d1
T_d2
T_d3
T_d4
T_de
RD
WEn ⋅
DQMxx
D31–D0
DACKn*
t_DQMD
t_DACD1
WAIT
RAS
t_RASD1
t_RASD1
CAS ⋅
OE
CKE
Note: * DACKn waveform when active-high is specified
Figure 22.20 Synchronous DRAM Read Bus Cycle
(Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle, CAS Latency = 1 Cycle)
Rev. 2.00 Mar 09, 2006 page 835 of 906
REJ09B0292-0200