SH7616 Datasheet, PDF (543/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
5. Before changing the frequency or changing to standby mode, set the DME bit of DMAOR to 0
and stop operation of the DMAC.
6. Do not use the DMAC, BSC, UBC, E-DMAC, and EtherC for on-chip peripheral module
transfers.
7. Do not access the cache (address array, data array, associative purge area).
8. Note that when level detection of the request signal is used in single address mode, the request
signal may be detected before DACKn is output.
9. When Eφ exceeds 31.25 MHz, do not use transfer involving DACKn output on ordinary space
for word or longword access with an 8-bit bus width, or longword access with a 16-bit bus
width.
10. When DMA transfer is performed in response to a DMA transfer request signal from a
peripheral module, if clearing of the DMA transfer request signal from the peripheral module
by the DMA transfer is not completed before the next transfer request signal from that module,
subsequent DMA transfers may not be possible.
11. The following restrictions apply when using dual address mode for 16-byte transfer in cycle-
steal mode:
a. When external request and level detection are set, do not input DREQn during cycles in
which DACKn is not active after the start of DMA transfer.
b. When external request DREQ edge detection is set, if DREQn is input continuously the
DMAC continues to operate without insertion of a CPU cycle. (However, a CPU cycle
will begin if there is no request from DREQn.)
Bus cycle
DACKn
(active high)
DREQn
(active high)
CPU
CPU
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(W)
DMA
(W)
DMA
(W)
DMA
(W)
CPU
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(W)
DMA
(W)
DMA
(W)
DMA
(W)
CPU
*
DACK output in read cycle
Bus cycle
CPU
CPU
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(W)
DMA
(W)
DMA
(W)
DMA
(W)
CPU
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(W)
DMA
(W)
DMA
(W)
DMA
(W)
CPU
DACKn
(active high)
DREQn
*
(active high)
DACK output in write cycle
Note: * In addition to CPU cycles, E-DMAC cycles may be inserted in some cases.
Rev. 2.00 Mar 09, 2006 page 517 of 906
REJ09B0292-0200