SH7616 Datasheet, PDF (184/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
Interrupt Source
Vectors
Vector
Vector Table
No.
Address
Interrupt
Priority
Order
(Initial
Value)
IPR (Bit
Numbers)
Priority
within
IPR
Setting VCR (Bit
Unit Numbers)
Default
Priority
SIOF
RERI0
TERI0
RDFI0
TDEI0
0–127^*2 VBR +
15–0 (0)
0–127^{*2 (vector No.}
0–127^{*2 × 4)}
0–127^*2
IPRE
(11–8)
High
↑
↓
Low
VCRP (14–8) High
VCRP (6–0) ↑
VCRQ (14–8)
VCRQ (6–0)
SIO1
RERI1
TERI1
RDFI1
TDEI1
0–127^*2
0–127^*2
0–127^*2
0–127^*2
15–0 (0) IPRE
(7–4)
High
↑
↓
Low
VCRR (14–8)
VCRR (6–0)
VCRS (14–8)
VCRS (6–0)
SIO2
RERI2
TERI2
RDFI2
TDEI2
0–127^*2
0–127^*2
0–127^*2
0–127^*2
15–0 (0) IPRE
(3–0)
High
↑
↓
Low
VCRT (14–8)
VCRT (6–0)
VCRU (14–8)
VCRU (6–0) ↓
Reserved
128–255 —
—
—
—
—
Low
Notes: 1. An external vector number fetch can be performed without using the auto-vector
numbers shown in this table. The external vector numbers are 0–127.
2. Vector numbers are set in the on-chip vector number register.
3. REF is the refresh control unit within the bus state controller.
4. Set to IRL1–IRL15 or IRQ0–IRQ3 by the EXIMD bit in ICR.
5. In the SH7616, VCRB is a reserved register and must not be accessed.
6. The E-DMAC interrupt (EINT) is the OR of those of the 19 interrupt sources in the
EtherC/E-DMAC status register (EESR) that are enabled by the EtherC/E-DMAC status
interrupt permission register (EESIPR). As the three status bits in the EtherC status
register (ECSR) can be copied into the ECI bit in EESR as an interrupt source, EINT is
input to the INTC as the OR of a maximum of 22 interrupt sources.
Rev. 2.00 Mar 09, 2006 page 158 of 906
REJ09B0292-0200