SH7616 Datasheet, PDF (306/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
16-bit external device (ordinary)
A24–A0 ^D15
000000 7
000001
000002 7
000003
000000 15
000002 15
000000 31
000002 15
D7
0
7
0
7
D0 _{Data input/output pin}
Byte read/write of address 0
0 Byte read/write of address 1
Byte read/write of address 2
0 Byte read/write of address 3
0 Word read/write of address 0
0 Word read/write of address 2
16
0 Longword read/write of address 0
Figure 7.6 16-Bit External Devices and Their Access Units
8-bit external device (ordinary)
A24–A0 ^D7
000000 7
000001 7
000002 7
000003 7
000000 15
000001 7
000002 15
000003 7
000000 31
000001 23
000002 15
000003 7
D0 _{Data input/output pin}
0 Byte read/write of address 0
0 Byte read/write of address 1
0 Byte read/write of address 2
0 Byte read/write of address 3
8
0 Word read/write of address 0
8
0 Word read/write of address 2
24
16
8
0 Longword read/write of address 0
Figure 7.7 8-Bit External Devices and Their Access Units
7.3.2 Connection to Little-Endian Devices
The chip provides a conversion function in CS2, CS4 space for connection to and to maintain data
compatibility with devices that use little-endian format (in which the LSB is the 0 position in the
byte data lineup). When the endian specification bit of BCR1 is set to 1, CS2, CS4 space is little-
endian. The relationship between device data width and access unit for little-endian format is
shown in figures 7.8, 7.9, and 7.10. When sharing memory or the like with a little-endian bus
master, the SH7616 connects D31–D24 to the least significant byte (LSB) of the other bus master
and D7–D0 to the most significant byte (MSB), when the bus width is 32 bits. When the width is
Rev. 2.00 Mar 09, 2006 page 280 of 906
REJ09B0292-0200