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SH7616 Datasheet, PDF (710/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
Section 17 16-Bit Timer Pulse Unit (TPU)
17.1.2 Block Diagram
Figure 17.1 shows a block diagram of the TPU.
Clock input
Internal clock: Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Channel 0:
Channel 1:
Channel 2:
I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TCR: Timer Control Register
TMDR: Timer Mode Register
TIOR: Timer I/O Control Register
TIER: Timer Interrupt Enable Register
TSR: Timer Status Register
TCNT: Timer Counter
TGR: Timer General Register
TSTR: Timer Start Register
TSYR: Timer Synchro Register
Figure 17.1 TPU Block Diagram
Internal data bus
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Rev. 2.00 Mar 09, 2006 page 684 of 906
REJ09B0292-0200