SH7616 Datasheet, PDF (687/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
Set to 1 when the amount of data in SITDR is
less than or equal to the setting of bits
TFWM3 to TFWM0 in SIFCR
TDRE
Synchronous internal clock
SITDR
C[7:0]
D[7:0]
Cleared to 0 when an amount of data exceeding
the setting of bits TFWM3 to TFWM0 in SIFCR
has been written to SITDR
D[7:0]
E[7:0]
SITSR
Undefined
C[0:7] C[1:7] C[2:7]
C[6:7] C[7] D[0:7] D[1:7] D[2:7]
STCK
STS
STXD
C[0] C[1] C[2]
C[6] C[7] D[0] D[1] D[2]
Note: TM = 1: STS is output
DL = 0: 8-bit data transfer
SE = 1: Synchronous transfer in start signal mode
LM = 1: LSB first
TRMD = 0: LSB of transmitted primary data is value in SITDR
Figure 15.12 Transmission: Interval Transfer Mode (TM = 1 Mode)/LSB First
Set to 1 when the amount of data in SITDR is
less than or equal to the setting of bits
TFWM3 to TFWM0 in SIFCR
TDRE
Synchronous internal clock
SITDR
C[7:0]
D[7:0]
Cleared to 0 when an amount of data exceeding
the setting of bits TFWM3 to TFWM0 in SIFCR
has been written to SITDR
D[7:0]
E[7:0]
SITSR
Undefined
C[0:7] C[1:7] C[2:7]
C[7] D[0:7] D[1:7] D[2:7] D[3:7]
STCK
STS
STXD
C[0] C[1] C[2]
C[7] D[0] D[1] D[2] D[3]
Note: TM = 1: STS is output
DL = 0: 8-bit data transfer
SE = 0: Asynchronous transfer, no start signal mode
LM = 1: LSB first
TRMD = 0: LSB of transmitted primary data is value in SITDR
Figure 15.13 Transmission: Continuous Transfer Mode (TM = 1 Mode)/LSB First
15.3.3 Output when TRMD = 1 in SIFCR
Figure 15.14 shows output timing when TM is set to 1 in SIFTR.
Rev. 2.00 Mar 09, 2006 page 661 of 906
REJ09B0292-0200