SH7616 Datasheet, PDF (251/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.2.17 Break Bus Cycle Register D (BBRD)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
XYED XYSD
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W
R/W
Bit:
Initial value:
R/W:
7
CPD1
0
R/W
6
CPD0
0
R/W
5
IDD1
0
R/W
4
IDD0
0
R/W
3
RWD1
0
R/W
2
RWD0
0
R/W
1
SZD1
0
R/W
0
SZD0
0
R/W
Break bus cycle register D (BBRD) is a 16-bit readable/writable register that sets five channel D
break conditions: (1) internal bus (C-bus, I-bus)/X memory bus/Y memory bus), (2) CPU
cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (3) instruction fetch/data access, (4) read/write,
and (5) operand size. BBRD is initialized to H'0000 by a power-on reset; after a manual reset, its
value is undefined.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 9—X/Y Memory Bus Enable D (XYED): Selects whether the X/Y bus is used as a channel D
break condition.
Bit 9: XYED
0
1
Description
Cache bus or internal bus is selected as condition for channel D address/data
(Initial value)
X/Y bus is selected as condition for channel D address/data
Bit 8—X Bus/Y Bus Select D (XYSD): Selects whether the X bus or the Y bus is used as a
channel D break condition. This bit is valid only when bit XYED = 1.
Bit 8: XYSD
0
1
Description
X bus is selected as channel D break condition
Y bus is selected as channel D break condition
(Initial value)
The configuration of bits 7 to 0 is the same as for BBRA.
Rev. 2.00 Mar 09, 2006 page 225 of 906
REJ09B0292-0200