SH7616 Datasheet, PDF (640/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Transmit/Receive Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are
added.
Clock: Either an internal clock generated by the built-in baud rate generator or an external serial
clock input at the SCK pin can be selected, according to the setting of the C/A bit in SCSMR and
the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 14.9.
When the SCIF is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no
transmission/reception is performed the clock is fixed high. In receive-only operation, however,
the SCIF receives two characters as one unit, and so a 16-pulse serial clock is output. To perform
single-character receive operations, an external clock should be selected as the clock source.
Transmit/Receive Operations
• SCIF Initialization (Synchronous Mode)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits to 0 in the
serial control register (SCSCR), then initialize the SCIF as described below.
When the operating mode, communication format, etc., is changed, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is
cleared to 0, the TDFE flag is set to 1 and the transmit shift register (SCTSR) is initialized.
Note that clearing the RE bit to 0 does not change the contents of the RDF, PER, FER, and
ORER flags, or the receive FIFO data register (SCFRDR).
Figure 14.17 shows a sample SCIF initialization flowchart.
Rev. 2.00 Mar 09, 2006 page 614 of 906
REJ09B0292-0200