SH7616 Datasheet, PDF (829/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 21 Power-Down Modes
21.2.2 Standby Control Register 2 (SBYCR2)
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
— MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6
(TPU) (SIO2) (SIO1) (SIOF) (SCIF2) (SCIF1)
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
Standby control register 2 (SBYCR2) is an 8-bit read/write register that sets the power-down mode
state. SBYCR2 is initialized to H'00 by a reset.
Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 5—Module Stop 11 (MSTP11): Specifies halting the clock supply to the 16-bit timer pulse
unit (TPU). When the MSTP11 bit is set to 1, the supply of the clock to the TPU is halted. When
the clock halts, the TPU retains its pre-halt state, and the TPU interrupt vector register in the INTC
retains its pre-halt value. Therefore, when MSTP11 is cleared to 0 and the clock supply to the TPU
is resumed, the TPU starts operating again.
Bit 5: MSTP11
0
1
Description
TPU running
Clock supply to TPU halted
(Initial value)
Bit 4—Module Stop 10 (MSTP10): Specifies halting the clock supply to SIO channel 2. When the
MSTP10 bit is set to 1, the supply of the clock to SIO channel 2 is halted. When the clock halts,
SIO channel 2 retains its pre-halt state, and the SIO channel 2 interrupt vector register in the INTC
retains its pre-halt value. Therefore, when MSTP10 is cleared to 0 and the clock supply to SIO
channel 2 is restarted, operation starts again.
Bit 4: MSTP10
0
1
Description
SIO channel 2 running
Clock supply to SIO channel 2 halted
(Initial value)
Rev. 2.00 Mar 09, 2006 page 803 of 906
REJ09B0292-0200