English
Language : 

SH7616 Datasheet, PDF (454/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit 19—Transmit FIFO Underflow (TFUF): Indicates that underflow has occurred in the transmit
FIFO during frame transmission. Incomplete data is sent onto the line.
Bit 19: TFUF
Description
0
Underflow has not occurred
(Initial value)
1
Underflow has occurred (interrupt source)
Note: Whether E-DMAC operation continues or halts after underflow is controlled by the E-DMAC
operation control register (EDOCR).
Bit 18—Frame Received (FR): Indicates that a frame has been received and the receive descriptor
has been updated. This bit is set to 1 each time a frame is received.
Note: The actual receive frame status is indicated in the receive status field in the descriptor.
Bit 18: FR
0
1
Description
Frame not received
Frame received (interrupt source)
(Initial value)
Bit 17—Receive Descriptor Exhausted (RDE): This bit is set if the receive descriptor active bit
(RACT) setting is “inactive” (RACT = 0) when the E-DMAC reads a receive descriptor.
Bit 17: RDE
Description
0
“1” receive descriptor active bit (RACT) detected
(Initial value)
1
“0” receive descriptor active bit (RACT) detected (interrupt source)
Note: When receive descriptor empty (RDE = 1) occurs, receiving can be restarted by setting
RACT = 1 in the receive descriptor and initiating receiving.
Bit 16—Receive FIFO Overflow (RFOF): Indicates that the receive FIFO has overflowed during
frame reception.
Bit 16: RFOF
Description
0
Overflow has not occurred
(Initial value)
1
Overflow has occurred (interrupt source)
Notes: 1. If there are a number of receive frames in the receive FIFO, they will not be sent to
memory correctly. The status of the frame that caused the overflow is written back to
the receive descriptor.
2. Whether E-DMAC operation continues or halts after overflow is controlled by the E-
DMAC operation control register (EDOCR).
Rev. 2.00 Mar 09, 2006 page 428 of 906
REJ09B0292-0200