SH7616 Datasheet, PDF (718/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3: Bit 2: Bit 1:
MD3^*1 MD2^*2 MD1
Bit 0:
MD0
Description
0
0
0
0
Normal operation
(Initial value)
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
1
0
0
Phase counting mode 1
1
Phase counting mode 2
1
0
Phase counting mode 3
1
Phase counting mode 4
1
*
*
*
—
*: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be
written to MD2.
17.2.3 Timer I/O Control Register (TIOR)
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Bit: 7
IOB3
Initial value: 0
R/W: R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
Channel 0: TIOR0L
Bit: 7
IOD3
Initial value: 0
R/W: R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
Rev. 2.00 Mar 09, 2006 page 692 of 906
REJ09B0292-0200