SH7616 Datasheet, PDF (220/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
5.6 Sampling of Pins IRL3–IRL0
Signals on interrupt pins IRL3 to IRL0 pass through the noise canceler before being sent by the
interrupt controller to the CPU as interrupt requests, as shown in figure 5.10. The noise canceler
cancels noise that changes in short cycles. The CPU samples the interrupt requests between
executing instructions. During this period, the noise canceler output changes according to the
noise-eliminated pin level, so the pin level must be held until the CPU samples it. This means that
interrupt sources generally must not be cleared inside interrupt routines.
When an external vector is fetched, the interrupt source can also be cleared when the external
vector fetch cycle is detected.
IRL0
IRL1
IRL2
IRL3
Noise
canceler
Interrupt
controller
Interrupt
request
Interrupt
accepted
CPU
IRL3–IRL0
pin level
1111
1011 for
1 clock
due to
noise
1111
Noise canceler
output
1111
Level 2 interrupt
1101
Level 6 interrupt
1001
Cleared when interrupt is accepted
1101
1001
Interrupt request
to CPU
Interrupt acceptance
signal from CPU
Figure 5.10 IRL3–IRL0 Pin Sampling
Rev. 2.00 Mar 09, 2006 page 194 of 906
REJ09B0292-0200