SH7616 Datasheet, PDF (221/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
5.7 Usage Notes
1. Note on module standby execution
Do not execute module standby for modules that have the module standby function when the
possibility remains that an interrupt request may be output.
2. Notes on interrupt source clearing
A. When clearing external interrupt source
If interrupt source clearing is performed by writing to an IO address (external), the next
instruction will be executed before completion of the write operation because of the write
buffer. To ensure that the write operation is completed before the next instruction is
executed, synchronization is achieved when a read is performed from the same address
following the write.
a. When returning from interrupt handling by means of RTE instruction
When the RTE instruction is used to return from interrupt handling, as shown in figure
5.11, consider the cycles to be inserted between the read instruction for synchronization
and the RTE instruction, according to the set clock ratio (Iφ : Eφ : Pφ) and external bus
cycle.
IRL3—IRL0 should be negated at least 0.5 Icyc + 1.0 Ecyc + 1.5 Pcyc before next
interrupt acceptance becomes possible.
For example, if clock ratio Iφ : Eφ : Pφ is 4 : 2 : 2, at least 5.5 Icyc should be inserted.
b. When changing level during interrupt handling
When the SR value is changed by means of an LDC instruction and multiple
implementation of other interrupts is enabled, also, consider the cycles to be inserted
between the synchronization instruction and the LDC instruction as shown in figure
5.12, according to the set clock ratio (Iφ : Eφ : Pφ) and external bus cycle.
IRL3–IRL0 should be negated at least 0.5 Icyc + 1.0 Ecyc + 1.5 Pcyc before next
interrupt acceptance becomes possible.
For example, if clock ratio Iφ : Eφ : Pφ is 4 : 2 : 2, at least 5.5 Icyc should be inserted.
Rev. 2.00 Mar 09, 2006 page 195 of 906
REJ09B0292-0200